TY  - THES
T1  - Complete formal hardware verification of interfaces for a FlexRay-like bus
A1  - Müller,Christian
Y1  - 2011/11/17
N2  - We report in this thesis the first complete formal verification of a bus interface at the gate and register level. The presented bus interface allows to implement a time- triggered system consisting of several units interconnected by a bus. Time-triggered systems work decentralized, allow some grade of fault-tolerance against a bounded number of single errors and show a predictable recurrent behaviour. We use a hardware model for multiple clock domains obtained by formalization of data sheets for hardware components, and we review known results and proof techniques about the essential components of such bus interfaces: among others serial interfaces, clock synchronization and bus control. Combining such results into a single proof leads to an amazingly subtle theory about the realization of direct connections between units (as assumed in existing correctness proofs for components of interfaces) by properly controlled time-triggered buses. It also requires an induction arguing simultaneously about bit transmission across clock domains, clock synchronization and bus control. The design of the bus controller can be automatically translated into Verilog and deployed on FPGAs.
KW  - FlexRay
KW  - Hardwareentwurf
KW  - Zeitgesteuertes System
KW  - Automotive
CY  - Saarbrücken
PB  - Universitäts- und Landesbibliothek
AD  - Postfach 151141, 66041 Saarbrücken
UR  - http://scidok.sulb.uni-saarland.de/volltexte/2011/4451
ER  -